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Espressif Systems /ESP32-P4 /SPI3 /SPI_USER2

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Interpret as SPI_USER2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPI_USR_COMMAND_VALUE0 (SPI_MST_REMPTY_ERR_END_EN)SPI_MST_REMPTY_ERR_END_EN 0SPI_USR_COMMAND_BITLEN

Description

SPI USER control register 2

Fields

SPI_USR_COMMAND_VALUE

The value of command. Can be configured in CONF state.
SPI_MST_REMPTY_ERR_END_EN

1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
SPI_USR_COMMAND_BITLEN

The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data